Silicon chip separation: Meeting demands of chip embedding packaging technology - eWLB

The objective of this paper is to present the key challenges in Silicon chip separation by mechanical dicing and changes needed in the saw street design to meet the additional demands in quality requirement put-forth by chip embedding packaging technology like the embedded Wafer Level Ball Grid array [eWLB]. When standard mechanical dicing process and saw street design meant for traditional packaging like wire bond or flip chip is used in assembly of chips in eWLB format, severe yield loss is observed at final test majority of them attributed to electrical short. Failure analysis of electrical shorts revealed metal burrs are in contact with redistribution layer [RDL] of the eWLB package. To overcome this issue, new saw street design has to be implemented in wafer fabrication and Silicon chip separation has to be optimized like blade selection and process parameters. After implementing these changes, Silicon chip separation process and eWLB assembly yield are monitored and final test yield shows elimination of electrical short failures. To date millions of eWLB packages housing highly integrated System on Chip Baseband processor, RF Transceiver, Power Management Unit and FM Radio manufactured in 65 nm technology node with new saw street design and Silicon chip separation process are shipped to our customers eventually ending up in hands of the consumers in the form of hand phone.