Title :
ARAS: asynchronous RISC architecture simulator
Author :
Chien, Chia-Hsing ; Franklin, Mark A. ; Pan, Tienyo ; Prabhu, Prithvi
Author_Institution :
Comput. & Commun. Res. Center, Washington Univ., St. Louis, MO, USA
Abstract :
In this paper, an asynchronous pipeline instruction simulator, ARAS is presented. With this simulator, one can design selected instruction pipelines and check their performance. Performance measurements of the pipeline configuration are obtained by simulating the execution of benchmark programs on the machine architectures developed. Depending on the simulation results obtained by using ARAS, the pipeline configuration can be altered to improve its performance. Thus, one can explore the design space of asynchronous pipeline architectures
Keywords :
parallel architectures; performance evaluation; pipeline processing; virtual machines; ARAS; asynchronous RISC architecture simulator; asynchronous pipeline architectures; benchmark programs; performance measurements; pipeline configuration; pipeline instruction simulator; Clocks; Computational modeling; Computer architecture; Design automation; Graphics; Microprocessors; Pipelines; Reduced instruction set computing; Space exploration; Visualization;
Conference_Titel :
Asynchronous Design Methodologies, 1995. Proceedings., Second Working Conference on
Conference_Location :
London
Print_ISBN :
0-8186-7098-3
DOI :
10.1109/WCADM.1995.514658
