Process challenges and development of eWLP

Author

Chong, Ser Choong ; Khong, Chee Houe ; Sing, Keith Lim Cheng ; Wee, David Ho Soon ; Liang, Calvin Teo Wei ; Sheng, Vincent Lee Wen ; Joon, Kim Hyoung ; Lee, Jaesik ; Rao, Vempati Srinivasa

Author_Institution

Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore

fYear

2010

fDate

8-10 Dec. 2010

Firstpage

527

Lastpage

531

Abstract

Embedded Wafer Level Package (eWLP) is designed and developed. The eWLP consists of one silicon die encapsulated with a mold compound and its size is 12mm × 12mm × 0.2mm. The assembly process of eWLP consists of reconfiguration of the dies on an adhesive tape, followed by molding, thinning and rerouting distribution layer (RDL) process. Finite Element Modeling (FEM) is used to understand the stress distribution in the eWLP and provide design input to the configuration of eWLP. The encapsulated eWLP passed 1000 air-to-air thermal cycles (-40 to 125°C), unbiased Highly Accelerated Stress Test (HAST) and moisture sensitivity level 3 (MSL3) test. In this paper, FEM of eWLP, selection of granular epoxy mold compound (EMC), die shift analysis, and warpage study will be discussed in detail.

Keywords

semiconductor device reliability; wafer level packaging; die shift analysis; eWLP; embedded wafer level package; finite element modeling; granular epoxy mold compound; process challenges; process development; rerouting distribution layer process; warpage study;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging Technology Conference (EPTC), 2010 12th

Conference_Location

Singapore

Print_ISBN

978-1-4244-8560-4

Electronic_ISBN

978-1-4244-8561-1

Type

conf

DOI

10.1109/EPTC.2010.5702696

Filename

5702696