DocumentCode :
2359176
Title :
Testing the path delay faults of ISCAS85 circuit c6288
Author :
Qiu, Wangqi ; Walker, D.M.H.
Author_Institution :
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
fYear :
2003
fDate :
29-30 May 2003
Firstpage :
19
Lastpage :
24
Abstract :
It is known that the ISCAS85 circuit c6288 contains an exponential number of paths and more than 99% of the path delay faults are untestable. Most ATPG tools, which can efficiently handle other circuits, fail on c6288. The logic structure ofc6288 is studied and the main features, which cause false paths, are revealed. A heuristic, which significantly helps the path delay fault test generation for this circuit, is presented. Experimental results show that our methodology is able to efficiently generate testable paths for c6288.
Keywords :
automatic test pattern generation; circuit testing; fault simulation; logic gates; ATPG tools; ISCAS85 circuit c6288; automatic test pattern generation; path delay fault testing; path generation; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Computer science; Delay effects; Logic; Resists; Test pattern generators; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microprocessor Test and Verification: Common Challenges and Solutions, 2003. Proceedings. 4th International Workshop on
Print_ISBN :
0-7695-2045-6
Type :
conf
DOI :
10.1109/MTV.2003.1250258
Filename :
1250258
Link To Document :
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