A methodology for validating manufacturing test vector suites for custom designed scan-based circuits

In Motorola´s High Performance Design Center, two verification flows are often used to verify correctness of custom designed blocks. The first is an equivalence checking flow, and the second is a manufacturing test pattern generation/simulation flow. The two flows are often disconnected resulting into silicon failures on manufacturing test vector suites. Our aim is to analyze the disconnect and to arrive at a technique that bridges the gap between the two verification flows by validating the correctness of manufacturing test patterns. This reduces time to market by cutting down on precious silicon debug time by eliminating redundant defect fixes. Our experimental results were obtained from a set of custom designed circuits of a Motorola MPC74XX microprocessor.