Comparison of double patterning technologies in NAND flash memory with sub-30nm node

Author

Hwang, Byungjoon ; Han, Jeehoon ; Kim, Myeong-Cheol ; Jung, Sunggon ; Lim, Namsu ; Jin, Sowi ; Yongsik Yim ; Kwak, Donghwa ; Park, Jaekwan ; Choi, Jungdal ; Kim, Kinam

Author_Institution

Semicond. R&D Center, Samsung Electron. Co. Ltd., Yongin, South Korea

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

269

Lastpage

271

Abstract

Fine patterning technologies - e-beam lithography, SPT (spacer patterning technology) and SaDPT (self aligned double patterning technology)-have been introduced to develop a single unit of nano-scale MOSFET. However, in order to achieve manufacturable high density NAND Flash memories, the merits and demerits of each technology should be considered in three points of view: device characteristics, process controllability and mass production. In this paper, we suggest the appropriate technology for particular cell types, CTF (charge trap flash) cell, floating poly-Si gate cell, and for process steps such as active, gate and bit-line.

Keywords

NAND circuits; electron beam lithography; elemental semiconductors; flash memories; nanopatterning; silicon; CTF cell; NAND flash memory; SPT; SaDPT; Si; active process; bit-line process; charge trap flash cell; e-beam lithography; floating poly-Si gate cell; gate process; self aligned double patterning technology; spacer patterning technology; Appropriate technology; Controllability; Electronic mail; Etching; Lithography; MOSFET circuits; Manufacturing processes; Mass production; Research and development; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European

Conference_Location

Athens

ISSN

1930-8876

Print_ISBN

978-1-4244-4351-2

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2009.5331401

Filename

5331401