Honeywell radiation hardened 32-bit processor single event effects test results

Author

Leavy, Scott C. ; Mogensen, Jeffrey A. ; Smith, Thomas S. ; Freitfeld, G.J. ; Brichacek, Julie

Author_Institution

Space Syst., Honeywell Inc., Clearwater, FL, USA

fYear

1998

fDate

36000

Firstpage

11

Lastpage

14

Abstract

We will present single event effects test results for the Honeywell radiation hardened 32-bit processor. The processor was tested at board-level while executing a signal and data processing benchmark suite

Keywords

CMOS digital integrated circuits; aircraft computers; fault tolerance; microprocessor chips; pipeline processing; proton effects; radiation hardening (electronics); reduced instruction set computing; space vehicle electronics; very high speed integrated circuits; 32 bit; CMOS very high speed IC; Honeywell radiation hardened processor; RISC; SEU performance; board-level test; data processing benchmark suite; fault-tolerant processor chipset; pipeline architecture; signal processing benchmark suite; single event effects test results; Aerospace electronics; Circuit faults; Circuit testing; Fault tolerance; Laboratories; Performance evaluation; Radiation hardening; Single event upset; Software testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Radiation Effects Data Workshop, 1998. IEEE

Conference_Location

Newport Beach, CA

Print_ISBN

0-7803-5109-6

Type

conf

DOI

10.1109/REDW.1998.731467

Filename

731467