Thermo-mechanical modeling of a 3D flip chip fully populated BGA package

In a flip chip package (FCBGA), the presence of stress arising from the thermal mismatch between different materials is inevitable. It is a challenge for the packaging community to manage these stresses via careful selection of materials and design to achieve optimal performance and reliability of the integrated circuit. Finite Element Analysis (FEA) modeling for thermomechanical study is a widely adopted tool to help predict the potential regions of stress. However, due to the huge computational effort and long solving time, the model is always simplified and represented in the form of symmetrical model, quarter model or strip model. This FEA technique is only valid if the package can meet the simplification requirements, for example, the geometry or solder bump layout, loads, constraints and material properties are symmetrical. However, this technique is not valid for asymmetrical constructions with fully populated solder bump or offset chip. Furthermore, the simplification technique comes with limitation to effectively identify full package high stress region and does not incorporate initial substrate warpage condition. Therefore, a 3D full package modeling technique is proposed to enhance existing simplification techniques and to improve the simulation accuracy. In this study, we used a 3D full package simulation modeling technique which also incorporates the initial substrate strip warpage condition and comparable copper trace details to examine fundamental characteristics of the flip chip package with the end in mind to minimize the stresses in the package. A parametric study on different die thicknesses, unit locations and substrate CTE was conducted to understand the impact on package and solder joint stress. Actual package samples were assembled to verify the simulation study results. Good correlation between the simulated and actual packaging results was achieved.