DocumentCode
2359777
Title
Reliability and failure analysis study of multi-die embedded micro wafer level packages
Author
Sekhar, V.N. ; Rao, V.S. ; Sharma, Gaurav ; Rajoo, Ranjan ; Ling, Serene Thew Mei ; Houe, Khong Chee ; Choong, Chong Ser ; Kuo, Cheng Cheng
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2010
fDate
8-10 Dec. 2010
Firstpage
668
Lastpage
672
Abstract
Main objective of this study is to design and development of multi-die embedded micro wafer level packages (EMWLP) reliability test vehicles. Such as, the laterally placed die EMWLP and the vertically stacked thin die EMWLP. For reliability evaluation, EMWLPs have been subjected to both environmental and mechanical reliability tests as per JEDEC standards. These reliability tests include highly accelerated stress testing (HAST), thermal Cycling (TC), moisture sensitivity testing level 3 (MSL3), board level TC and drop tests. In case of drop tests evaluation, two types of pad finishes, ENIG & OSP have been used. During reliability tests both test vehicles have exhibited better performance without any electrical failures. But in case of HAST reliability test, delamination issue in two packages have been observed. Detailed failure analysis has been carried out on delaminated packages to find out the root cause for the different modes of delamination failures. Non-destructive and destructive techniques have been employed to investigate the failures in EMWLP´s and this includes electrical testing, Scanning Acoustic Microscopy (SAM), micro-sectioning and Scanning Electron Microscopy (SEM). Delamination interface has been identified as passivation-RDL interface. Thermo-mechanical simulation study has been carried out over both test vehicles to locate higher stress concentration regions in the packages and finally to correlate with experimental reliability and failure analysis results.
Keywords
acoustic microscopy; delamination; failure analysis; integrated circuit design; integrated circuit reliability; integrated circuit testing; scanning electron microscopy; wafer level packaging; EMWLP; ENIG; JEDEC standards; OSP; electrical testing; failure analysis; highly accelerated stress testing; micro-sectioning; moisture sensitivity testing level 3; multi-die embedded micro wafer level packages; non-destructive techniques; passivation-RDL interface; reliability; scanning acoustic microscopy; scanning electron microscopy; thermal cycling; thermo-mechanical simulation;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference (EPTC), 2010 12th
Conference_Location
Singapore
Print_ISBN
978-1-4244-8560-4
Electronic_ISBN
978-1-4244-8561-1
Type
conf
DOI
10.1109/EPTC.2010.5702722
Filename
5702722
Link To Document