VLSI Architecture of Video Post-Processing System for MPEG/H.26X

A novel VLSI architecture for digital multimedia post-processing system is presented. First, the sequence of the post-processing de-blocking filter is modified, and the filter algorithm is optimized. Second, the frames are extended at the upper and left frame boundaries for 8 pixels in depth in order to avoid the irregularity and simplify the control unit. At last a macro block-based together with block-based double pipelining design technology is adopted to improve efficiency of data flow control scheme and parallel calculation, and to improve the real time performance. 8-bit wide dual-port reading and writing at the same time memories are used to optimize the data storage structure, which effectively reducing hardware expenditure. Experiment results show that the proposed design has capability to process HDTV1080P 30-fps video at 108 MHZ and achieves at least 5% hardware expenditure reduction comparing with existing designs.