• DocumentCode
    2360012
  • Title

    Design and Simulation of Logic Circuits with Hybrid Architectures of Single Electron Transistors and Conventional Devices

  • Author

    Venkataratnam, A. ; Goel, A.K.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI
  • fYear
    2006
  • fDate
    Sept. 2006
  • Firstpage
    1
  • Lastpage
    5
  • Abstract
    Single electron transistor is a nanoelectronic three terminal device. It provides current conduction characteristics comparable to a MOSFET. In this paper, the authors have designed and simulated logic circuit architectures with a combination of SET and conventional devices such as MOSFETs and comparators. The performances of these hybrid architectures and their advantages and disadvantages with SET standalone circuits have also been studied
  • Keywords
    CMOS integrated circuits; logic circuits; logic design; single electron transistors; CMOS devices; MOSFET; logic circuits; single electron transistors; Capacitance; Circuit simulation; Logic circuits; MOSFETs; Nanoscale devices; SPICE; Single electron transistors; Temperature; Tunneling; Voltage; CMOS; Hybrid; SET; SPICE;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on
  • Conference_Location
    Lausanne
  • Print_ISBN
    1-4244-0391-X
  • Type

    conf

  • DOI
    10.1109/NANONET.2006.346218
  • Filename
    4152801
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2360012