BGA package design for reduced gold bond wire length and package parasitics with etch-back process

An approach to simultaneously reduce the length of bond wires and trace parasitics within substrate-based, chip-on-board (COB), ball grid array (BGA) packages is presented. Three, two-layer, 8mm × 14mm COB BGA packages were modeled and analyzed using Ansoft Turbo Package Analyzer´s (TPA) 3D boundary element method (BEM). The initial package design has long interconnecting bond wires from the die to the substrate´s bond fingers. This results in higher costs and parasitic effects that are detrimental to high-speed performance. To shorten the length of interconnecting bond wire per I/O, bond fingers are repositioned nearer to the die. However, this results in long plating stubs that contribute to capacitive parasitic and emits spurious EM radiation. Implementing an etch-back process during substrate fabrication removes these undesirable effects. Results show that trace parasitic capacitance, inductance, and resistance can be reduced by as much as 50%, 35%, and 32%, respectively.