Title :
3D on-chip networking technology based on post-silicon devices for future networks-on-chip
Author :
Fujita, Shinobu ; Nomura, Kumiko ; Abe, Keiko ; Lee, Thomas H.
Author_Institution :
Frontier Res. Lab., Toshiba Corp., Kawasaki
Abstract :
We propose a 3D architecture using post-silicon devices, such as nano-mechanical electrical switches, carbon nanotube FETs, and nanowire FETs, for future networks-on-chip (NoC). Based on such a new 3D architecture, extremely high bandwidth with very low latency can be realized. These promising features are very useful for future NoCs
Keywords :
nanotechnology; network-on-chip; 3D architecture; 3D on-chip networking technology; NoC; networks-on-chip; post-silicon devices; Bandwidth; CMOS technology; Delay; Electronic mail; Integrated circuit interconnections; Nanoscale devices; Network-on-a-chip; Page description languages; Space technology; Wire; NEMS; carbon nanotube; component: 3D circuit; interconnect delay; nano-mechanical electrical system; nanowire; post-silicon;
Conference_Titel :
Nano-Networks and Workshops, 2006. NanoNet '06. 1st International Conference on
Conference_Location :
Lausanne
Print_ISBN :
1-4244-0391-X
DOI :
10.1109/NANONET.2006.346233
