DocumentCode
2360595
Title
An architecture for the implementation of a parallel marker propagation system
Author
Schneider, Howard
Author_Institution
Dept. of Psychiatry, Cite de la Sante de Laval Hospital, Laval, Que., Canada
fYear
1988
fDate
10-12 Oct 1988
Firstpage
525
Lastpage
529
Abstract
An architecture is proposed which allows the construction of massively parallel (i.e. multibillion node, multi-trillion linked) marker propagation systems. The nodes used in this architecture allow the best intersection of markers to be found by comparing the contents of the intersection register with the descending values on the control word bus. The physical implementation consists of a silicon structure which is composed of 20000 functional planes of silicon-based circuitry, interconnected by 5 billion vertical interconnecting wires. Any node can be linked directly with any other node
Keywords
multiprocessor interconnection networks; parallel architectures; control word bus; descending values; functional planes; intersection register; parallel marker propagation system; silicon structure; Circuits; Computer architecture; Concurrent computing; Detectors; Fasteners; Hospitals; Information retrieval; Power system interconnection; Psychiatry; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Frontiers of Massively Parallel Computation, 1988. Proceedings., 2nd Symposium on the Frontiers of
Conference_Location
Fairfax, VA
Print_ISBN
0-8186-5892-4
Type
conf
DOI
10.1109/FMPC.1988.47492
Filename
47492
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