Gate-All-Around technology: taking advantage of ballistic transport ?

Author

Bidal, G. ; Huguenin, J.L. ; Denorme, S. ; Fleury, D. ; Loubet, N. ; Ydebasque, A. Pou ; Perreau, P. ; Leverd, F. ; Barnola, S. ; Beneyton, R. ; Orlando, B. ; Gouraud, P. ; Salveta, T. ; Clement, L. ; Monfray, S. ; Ghibaudo, G. ; Boeuf, F. ; Skotnicki, T.

Author_Institution

STMicroelectronics, Crolles, France

fYear

2009

fDate

14-18 Sept. 2009

Firstpage

315

Lastpage

318

Abstract

This work presents an experimental study in order to evaluate the quality of transport in state-of-the-art gate-all-around devices. 25 nm times 20 nm times 10 nm (LxWxT_Si) silicon channel devices with metal/high-k gate all-round stack were characterized electrically in terms of mobility and limiting velocity in order to evaluate the possible occurrence of ballisticity. Conclusions are finally presented in the scope of elementary circuit perspectives.

Keywords

ballistic transport; carrier mobility; elemental semiconductors; semiconductor devices; silicon; Si; ballistic transport; electrical mobility; elementary circuit perspectives; gate-all-around devices; limiting velocity; metal-high-k gate all-round stack; silicon channel devices; size 10 nm; size 20 nm; size 25 nm; Backscatter; Ballistic transport; Degradation; Doping; MOSFET circuits; Nanoscale devices; Particle scattering; Rough surfaces; Silicon; Surface roughness;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid State Device Research Conference, 2009. ESSDERC '09. Proceedings of the European

Conference_Location

Athens

ISSN

1930-8876

Print_ISBN

978-1-4244-4351-2

Electronic_ISBN

1930-8876

Type

conf

DOI

10.1109/ESSDERC.2009.5331466

Filename

5331466