Study of the effects of SET induced faults on submicron technologies

The progression of shrinking technologies into processes below 100nm has increased the importance of transient faults in digital systems. Fault injection into the HDL model of the system, known as simulation-based fault injection, is being increasingly used in recent years in order to evaluate the behaviour of systems in the presence of transient faults. However, there are still several questions in conducting simulation-based fault injections. For instance, what is the importance of timing information of the netlist with regard to the accuracy of fault injection results? And how does the number of fault injection experiments relate to obtain a realistic behaviour of the processor under test. Finally, what is the dependence of fault injection results on the processor´s workload? This paper aims to answer these questions, by studying the effects of transient faults on a post placed-and-routed Verilog netlist of a high performance reconfigurable processor in 90-nanometer UMC technology.