Challenges for silicon technology scaling in the nanoscale era

The continuous and systematic increase in transistor density and performance, as described in ldquoMoore´s Lawrdquo and guided by CMOS scaling theory, has been remarkably successful for the development of silicon technology for the past 40 years. As the silicon industry moves into sub-ten nanometer dimensions, significant technology challenges in device performance, power dissipation, and variability will be imposed by the approach toward atomistic and quantum-mechanical physics boundaries. These issues are frequently cited as the reason Moore´s Law is ldquobrokenrdquo, or why CMOS scaling is coming to an end. However, the infusion of new materials, device structures, and the exploitation of 3D-silicon integration, coupled with innovations in circuit design and system architecture, will ensure several more generations of continued CMOS development.