Investigating the impact of process variations on an asynchronous Time-Triggered-Protocol controller

In recent years, asynchronous logic has often been used as feasible alternative to common synchronous logic design. However, changing the basic design paradigm from using a global clock signal (in order to hide all timing constraints and assumptions behind it) to the technique of local handshaking protocols is not always easy. The automatic adaption to changing operating conditions (“it runs as fast as possible”) also makes reliable timing predictions rather complex. While this might be an advantage for many applications, especially real-time systems need a precise, predictable and reliable notion of time, and continuously changing operating speeds are undesired. In this work we experimentally investigate the impact of process/fabrication variations on the execution speed and frequency stability of our asynchronous Time-Triggered-Protocol controller. We use a set of modern FPGA development boards and analyze the variations of important circuit-level properties such as execution speed, jitter characteristics and frequency stability. The measurement results are also compared to the expectations derived from the device timing data sheets and the respective post-layout simulations.