An accurate approach for statistical estimation of leakage current considering multi-parameter process variations in nanometer CMOS technologies

The dramatic increase in leakage current has become a major issue for future IC design. Moreover, as process variability in nano-scaled CMOS technologies induces a large spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for CMOS circuit leakage under statistical process variations. The developed methodology is integrated with standard BSIM4 and PSP transistor model, and applicable to any CMOS technologies (90 nm, 65 nm, 45 nm), and SPICE simulators. Subthreshold, gate, BTBT, and GIDL leakage currents variations are considered. Comparisons with Monte-Carlo simulations on 45 nm STMicroelectronics CMOS technologies fully validate the accuracy and efficiency of the proposed method.