Title :
VHDL Model Of High-Speed Single-Port RAM (Synchronous Type)
Author_Institution :
Transilvania University
Keywords :
Circuit testing; Clocks; Electronic equipment; Electronic equipment testing; Lakes; Logic testing; Microprocessors; Random access memory; Read-write memory; System testing;
Conference_Titel :
Optimization of Electrical and Electronic Equipments, 1998. OPTIM '98. Proceedings of the 6th International Conference on
Conference_Location :
Brasov, Romania
Print_ISBN :
973-98511-2-6
DOI :
10.1109/OPTIM.1998.708012
