DocumentCode
2361650
Title
Beyond cost-of-ownership: a causal methodology for costing wafer processing
Author
Miraglia, Stephanie ; Miller, Peter ; Richardson, Thomas ; Blunt, Gregory ; Blouin, Cathy
Author_Institution
Microelectron. Div., IBM Corp., Essex Junction, VT, USA
fYear
1998
fDate
23-25 Sep 1998
Firstpage
289
Lastpage
293
Abstract
Classical cost-of-ownership data provides detailed cost data of equipment assets but does not provide wafer processing costs. Starting with a cost-of-ownership model, a wafer processing cost model was developed and validated. This cost-of-processing model provides wafer processing cost data from raw wafer through final passivation and parametric testing. This new model goes beyond classical cost-of-ownership data and captures more than just equipment costs-process, product, and fabricator costs are also captured. These costs are then causally spread to wafers via various algorithmic methodologies. In order to do this, some historical cost problems had to be addressed, such as how to properly weight equipment usage and account for dedicated equipment requirements, deal with measurement sampling, incorporate idle time and contingency, and account for different photolithographic field sizes. Output from the model was fully validated against actual spending and tied to accounting data in order to assure a full dollar capture. The model is currently being used for product costing, decision making, and cost reduction activities at the IBM Microelectronics Division Manufacturing Facility in Essex Junction, Vermont
Keywords
costing; integrated circuit manufacture; integrated circuit measurement; passivation; photolithography; sampling methods; algorithmic methodologies; causal cost spreading; causal methodology; contingency; cost data; cost reduction; cost-of-ownership; cost-of-ownership data; cost-of-ownership model; cost-of-processing model; costing; decision making; dedicated equipment requirements; equipment asset costs; equipment costs; equipment usage weighting; fabricator costs; final passivation; idle time; measurement sampling; model validation; parametric testing; photolithographic field sizes; process costs; product costing; product costs; raw wafer; wafer processing; wafer processing cost data; wafer processing cost model; wafer processing costs; Costing; Costs; Decision making; Microelectronics; Passivation; Sampling methods; Semiconductor device modeling; Size measurement; Testing; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location
Boston, MA
ISSN
1078-8743
Print_ISBN
0-7803-4380-8
Type
conf
DOI
10.1109/ASMC.1998.731573
Filename
731573
Link To Document