Title :
A study in the continuous improvement process: implementation of an optimized scrubber to replace TEOS backside etch post SOG etchback
Author :
Au, W. ; Parks, D. ; Esquivel, P.
Author_Institution :
VLSI Technol. Inc., San Antonio, TX, USA
Abstract :
As device features become smaller and manufacturing processes get more complicated, exploration of ways to reduce the number of process steps is gaining serious attention. This allows the manufacturing company to remain competitive within the semiconductor industry. This paper describes a continuous improvement process through the implementation of a scrubber post SOG etchback to remove TEOS backside etch. As the particle level of the wafer backside increases after SOG etchback, TEOS backside etch was done to clean the wafer backside to minimize focusing error in subsequent photolithography steps. The module involves resist coating of the wafer front side, a buffer HF oxide etch, followed by the resist ash and strip. Replacing the entire module with a backside scrub offers significant chemical cost savings, process cycle time reduction and increased sink, coater and asher capacity. Detailed descriptions of the old and new process and a comparison of particle and yield data are presented. Overall improvement in the manufacturing process is demonstrated by measures of cycle time, chemical cost, personnel efficiency, reduction in equipment purchases, and fab capacity
Keywords :
etching; glass; integrated circuit measurement; integrated circuit reliability; integrated circuit yield; photolithography; spin coating; surface cleaning; surface contamination; HF; SiO2-Si; TEOS backside etch; TEOS backside etch replacement; asher capacity; backside scrub; buffer HF oxide etch; chemical cost; chemical cost savings; coater capacity; competitiveness; continuous improvement process; cycle time; device feature size; equipment purchases; fab capacity; focusing error minimization; manufacturing process; manufacturing process complexity; optimized scrubber implementation; particle data; personnel efficiency; photolithography; post SOG etchback; process cycle time reduction; process steps; resist ash; resist coating; resist strip; semiconductor industry; sink capacity; wafer backside cleaning; wafer backside particle level; wafer front side resist coating; yield data; Chemical processes; Coatings; Continuous improvement; Costs; Electronics industry; Etching; Lithography; Manufacturing processes; Resists; Semiconductor device manufacture;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731574