Title :
Effects of photoresist foreshortening on an advanced Ti/AlCu/Ti metallurgy and W interconnect technology
Author :
Whiteside, Cynthia ; Rutten, Matt ; Trombley, Henry ; Landis, Howard ; Boltz, Michelle
Author_Institution :
IBM Corp., Essex Junction, VT, USA
Abstract :
Competitive technology ground rules for BEOL (Back end of Line) interconnects have been shrinking aggressively. Extending the life of existing tool sets and manufacturing processes for these new aggressive technologies is required to make these newer technologes cost competitive. This paper describes the early process transfer phase of a technology installation into a manufacturing. The effects of photolithography induced metal line end shortening foreshortening) can have a significant impact on the etched Ti/AlCu/Ti/TiN metal lines (Figure 1). This defect observed after metal etch is directly attributed to foreshortening of the photoresist lines. When a tungsten contact (interconnect) is not fully covered by a resist line during the metal etch and subsequent chromic phosphoric clean operation, attack of the Ti/AlCu/Ti metallurgy occurred. The metal defect resulted in test yield loss due to open metal line and high via resistance which impacted wafer final test yield. This defect was found to impact single metal to via interfaces within small via chain defect monitors which lead to serious reliability concerns due to the low level of detectability for this problem on products.
Keywords :
aluminium alloys; copper alloys; etching; integrated circuit interconnections; integrated circuit metallisation; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; integrated circuit yield; photolithography; photoresists; reticles; titanium; tungsten; AlCu-W; Ti-AlCu-Ti metallurgy; Ti-AlCu-Ti metallurgy/W interconnect technology; Ti-AlCu-Ti-TiN; W contact; W interconnect; chromic phosphoric clean; defect detectability; design ground rule violations; etched Ti-AlCu-Ti-TiN metal lines; foreshortening mechanism; high via resistance; line end extensions; line extension modelling; line flare modelling; lithography-driven resist line foreshortening; manufacturing controls; mask design; metal etch; metal line; metal line flaring; metal-via interface; open metal lines; photolithography induced metal line end shortening; photoresist foreshortening effects; photoresist line foreshortening; process line; process sensitivities; reliability; resist line; resist line slope; reticle design; robust process window; single metal-via interfaces; test data; test yield loss; via chain defect monitors; via coverage; Costs; Etching; Focusing; LAN interconnection; Lenses; Lithography; Manufacturing processes; Microelectronics; Resists; Testing;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA, USA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731584