Title :
On partitioning for pseudo exhaustive testing of VLSI circuits
Author :
Jone, Wen-Ben ; Papachristou, C.A.
Author_Institution :
Dept. of Comput. Sci., New Mexico Inst. of Min. & Technol., Socorro, NM, USA
Abstract :
The authors propose an algorithm to partition a given circuit into a set of subcircuits such that pseudoexhaustive self-testing will be possible. The algorithm is based on a graph-theoretic model using the concept of minimum vertex cut to maintain a tolerable hardware overhead. Experiment by computer simulation has been conducted and the results demonstrate that the proposed method is effective, particularly for circuits which are highly locally connected
Keywords :
VLSI; digital simulation; graph theory; integrated circuit testing; VLSI circuits; algorithm; computer simulation; graph-theoretic model; minimum vertex cut; partitioning; pseudoexhaustive self-testing; Automatic testing; Built-in self-test; CMOS logic circuits; Circuit faults; Circuit testing; Computer simulation; Hardware; Integrated circuit interconnections; Partitioning algorithms; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1988., IEEE International Symposium on
Conference_Location :
Espoo
DOI :
10.1109/ISCAS.1988.15295
