Fast analysis of on-chip power distribution networks

The verification of the power distribution network is of critical importance to ensure reliable performance. However, with the increasing number of transistors on a chip, the complexity of the power network has also grown. The available computational power and memory resources impose limitations on the size of the networks that can be analyzed using currently known techniques. In this paper, we present a fast and efficient method to analyze power distribution networks in the time-domain. The new contributions of this work are the use of PWL data point reduction and correction factors (CF) to reduce the number of current source models and to speed up the characterization time. The proposed techniques provide good analysis results compared to the reference with a reduction of the run-time by a factor of 400, although the cell pre-characterization is based on SPICE simulations. Our model is independent of power network parasitics, which implies that different power network scenarios may be analyzed based on the same model and the same cell characterizations. The runtime and accuracy of the proposed approach are demonstrated on some industrial designs.