Title :
Performance analysis of full adder (FA) cells
Author :
Yen, Phuong Thi ; Abidin, Noor Faizah Zainul ; Ghazali, Azrul Bin
Author_Institution :
Dept. of Electron. & Commun., Univ. Tenaga Nasional, Kajang, Malaysia
Abstract :
Since full adders play a vital role in electronics design, new ideas, investigations and study cases for constructing full-adders are required. This paper presents a comprehensive study of 24 different single-bit full adder (FA) topologies. All FA cells are designed using 0.18μm Silterra transistor models. Each FA cell is analyzed in terms of power and delay. The design and simulation of each FA cell are performed using Hspice simulator. The results of this paper are expected to assist designers to select the appropriate FA cell that meets their specific applications.
Keywords :
SPICE; adders; transistors; Hspice simulator; Silterra transistor models; full adder cells; single-bit full adder topologies; size 0.18 mum; Adders; Delay; Logic gates; Performance evaluation; Power demand; Transistors; Very large scale integration;
Conference_Titel :
Computers & Informatics (ISCI), 2011 IEEE Symposium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-61284-689-7
DOI :
10.1109/ISCI.2011.5958899
