Power transistor design guidelines and RF load-pull characterization of a 0.13-µm SOI CMOS technology

In this work, the RF power performance of a 0.13-mum partially depleted SOI CMOS technology is explored. To this end, a prototype 1-mm-width power transistor has been designed and fabricated for multi-harmonic load-pull characterization. The device tolerance to single-transistor latch-up under large-signal conditions has been considered as the key design issue for safe operation in RF power applications. Proper design criteria have been derived and the length of the gate fingers has been chosen accordingly. The test device achieves a 72% power-added efficiency and a 19.5-dBm output power level, while operating at a 2-V supply voltage under 1.9-GHz continuous-wave excitation.