DocumentCode :
2362465
Title :
New QC-LDPC codes implementation on FPGA platform in Rayleigh fading environment
Author :
Ghani, Farid ; Yahya, Abid ; Kader, Abdul
Author_Institution :
Sch. of Comput. & Commun. Eng., Univ. Malaysia Perlis (UniMAP), Kuala Perlis, Malaysia
fYear :
2011
fDate :
20-23 March 2011
Firstpage :
206
Lastpage :
210
Abstract :
This paper presents performance of Quasi-Cyclic low-density parity-check (QC-LDPC) codes on a flat Rayleigh fading channels by employing DPSK modulation scheme. The BER curves show that large girth and diversity level robust the system performance. Moreover, Prototype architecture of the LDPC codes has been implemented by writing Hardware Description Language (VHDL) code and targeted to a Xilinx Spartan-3E XC3S500E FPGA chip. Simulation results show that the proposed QC-LDPC codes achieve a 0.1dB coding gain over randomly constructed codes and perform 1.3 dB from the Shannon-limit at a BER of 10-6 with a code rate of 0.89 for block length of 1332.
Keywords :
Rayleigh channels; cyclic codes; differential phase shift keying; error statistics; field programmable gate arrays; hardware description languages; parity check codes; BER; DPSK modulation scheme; QC-LDPC codes implementation; VHDL code; Xilinx Spartan-3E XC3S500E FPGA chip; flat Rayleigh fading channels; gain 0.1 dB; hardware description language code; quasi-cyclic low-density parity-check codes; Bit error rate; Channel coding; Decoding; Fading; Field programmable gate arrays; Parity check codes; Bit error rate; Communication channels; Encoding; FPGA; QC-LDPC; Rayleigh Fading;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computers & Informatics (ISCI), 2011 IEEE Symposium on
Conference_Location :
Kuala Lumpur
Print_ISBN :
978-1-61284-689-7
Type :
conf
DOI :
10.1109/ISCI.2011.5958912
Filename :
5958912
Link To Document :
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