FPGA implementation of DSSS-CDMA transmitter and receiver for ADHOC networks

The DS - CDMA is expected to be the major medium access technology in the future mobile systems owing to its potential capacity enhancement and the robustness against noise. The CDMA is uniquely featured by its spectrum-spreading randomization process employing a pseudo-noise (PN) sequence, thus is often called the spread spectrum multiple access (SSMA). As different CDMA users take different PN sequences, each CDMA receiver can discriminate and detect its own signal, by regarding the signals transmitted by other users as noise-like interferences. In this project Direct sequence principle based CDMA transmitter and receiver is implemented in VHDL for FPGA. The digital frequency synthesizer principle is used in generating the carrier signals both at transmitter and receiver modules. The transmitter module mainly consists of symbol generator, programmable PN sequence generator, digital local oscillator, spreader and BPSK modulator blocks. The receiver module consists of BPSK demodulator, matched filter, programmable PN sequence generator and threshold detector blocks. The CDMA receiver gets this input and recovers the data using matched filter. Modlesim Xilinx Edition 5.8 (MXE) tool will be used for functional simulation and logic verification at each block level and system level. The Xilinx Synthesis Technology (XST) of Xilinx ISE tool will be used for synthesis of transmitter and receiver on FPGAs. Applications of the developed CDMA system for ADHOC networks and defense communication links will be studied. The possible extensions of work in view of advancements in software defined radio principles will be discussed.