Title :
A manufacturable shallow trench isolation process for 0.18 μm and beyond-optimization, stress reduction and electrical performance
Author :
Nouri, F. ; Laparra, O. ; Sur, H. ; Tai, G.C. ; Pramanik, D. ; Manley, M.
Author_Institution :
Technol. Dev., VLSI Technol. Inc., San Jose, CA, USA
Abstract :
An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 μm technologies
Keywords :
circuit optimisation; integrated circuit design; integrated circuit manufacture; internal stresses; isolation technology; leakage currents; oxidation; plasma materials processing; thermal analysis; thermal stresses; 0.18 micron; HDP oxide; STI optimization; STI process; Si; SiO2-Si; electrical performance; high density plasma oxide; integrated shallow trench isolation process; junction leakage; manufacturability; manufacturable corner oxidation; manufacturable shallow trench isolation process; multi-million gate designs; optimal design; process robustness; silicon stress; stress reduction; trench corner oxidation temperature; trench depth; well profiles; well-edge isolation; Application specific integrated circuits; Etching; Implants; Isolation technology; Manufacturing processes; Oxidation; Planarization; Plasma temperature; Silicon; Stress;
Conference_Titel :
Advanced Semiconductor Manufacturing Conference and Workshop, 1998. 1998 IEEE/SEMI
Conference_Location :
Boston, MA
Print_ISBN :
0-7803-4380-8
DOI :
10.1109/ASMC.1998.731638
