On the integration of Ta2O5 as a gate dielectric in sub-0.18 μm CMOS processes

In this paper, a feasibility study on the incorporation of Ta₂O₅ as a gate dielectric in sub-0.18 μm CMOS processes is presented. The advantages of such a structure are investigated and appear consistent with low voltage/high performance applications. The main technological features associated with this incorporation are discussed (Ta₂O₅ densification and interfacial oxide, gate electrode and related features, etching, TiN behaviour, etc.) and a full process flow with few modifications with respect to standard CMOS is presented. With this flow, real devices were processed and their electrical characteristics are shown. These results are close to current SiO₂ MOS results, and are therefore promising for sub-2.5 nm equivalent SiO₂ thickness gate dielectrics