SIMD architecture for image segmentation using Sobel operators implemented in FPGA technology

In this paper, we present a SIMD architecture implemented on FPGA devices, this architecture is based on parallel processing units with internal pipeline and uses Sobel gradient operators for edge detection, we also show an application for electronic boards images with surface mount devices. This architecture takes advantage of the FPGA´s capabilities for parallel processing in order to reduce the time needed using a sequential machine. The proposed architecture is able to segment up to 43 images of 640×480 pixels in one second with 40 MHz clock frequency.