Strained and unstrained Si nanowire FETs

Recent experimental results on Si nanowire MOSFETs are presented. The devices were fabricated in a top-down approach on unstrained and biaxial strained SOI substrates exhibiting good I-V characteristics with I_on/I_off-ratios of 10⁷ and off-currents as low as 10^-13 A. Subthreshold slopes of about 70 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-FETs fabricated on strained SOI substrates are 2.5 and 2.1 times larger, respectively, due to the uniaxial tensile strain along the wires. Moreover, current transport on surfaces with different crystal orientation in NWs is employed to match on-currents of SOI n- and p-FETs.