A highly reliable multilevel interconnection process for 0.6 μm CMOS devices

The authors describe a noble interconnection process technology for 0.6 μm CMOS devices. The line and space are 0.6 μm/0.6 μm for the first metal and 1.0 μm/0.8 μm for the second metal. Contact holes with a diameter of 0.7 μm are filled with W-plugs using blanket CVD-W and the subsequent etching back process. The via hole size is 0.7 μm in diameter. A multilayered metallization structure consisting of TiN(35 nm)/W(65 nm)/Al-0.5 % Cu(400 nm) is applied. W film is formed on AlCu alloy to provide against a stress migration failure, while TiN film is used as an anti-reflecting coating (ARC). For the interlevel dielectric TEOS-O₃ APCVD oxide with superior self-filling capability is employed, resulting in a significant process latitude in photolithography of the second metal. Electromigration life time of the multilayered metallization system is longer than that of AlSiCu interconnect by one order of magnitude under a stress condition of 1×10⁶ A/cm² at 200°C. The mean time to failure(MTTF) of via hole chains is more than 2000 hours under the same stress condition. No open-circuit failure occurs after the stress migration test for 3000 hours at 200°C for both the metal lines and the via hole chains