A simple and efficient VLSI architecture for a very fast high performance three step search algorithm

In this paper, we design a simple and efficient VLSI architecture for a novel very fast high performance three step search (FHTSS) algorithm that is superior to the existing three step search (TSS) algorithm in all cases and also to the recently proposed new three step search (NTSS) algorithm when used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the FHTSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three step search algorithms