The backend process integration of an advanced double metal technology for sub-μm high-speed CMOS and BiCMOS SRAM

A double metal double poly technology has been built up for the Winbond twin-tub 0.8 μm CMOS and Bi-CMOS processes, which were developed for applications of 256K and 1 M high speed SRAM. This state-of-the art backend process technology includes: (a) non-etch back siloxane SOG planarization; (b) reactive sputtering TiN barrier metal; (c) sputtered anti-reflective coating (ARC); (d) i-line stepper lithography with phase grating alignment; and (e) low hydrogen content PECVD nitride passivation. To achieve high speed performance, RC delay is one of major concerns. It is particularly true when using non-etch back organic SOG as planarization material between metal interconnects. The improper process control would drastically deteriorate the characteristics of parasitic intermetal capacitance or increase the via resistance. The small metal pitch and contact/via size would also increase the possibility of electromigration. In addition, the hydrogen released from conventional PECVD nitride film could affect poly load resistance and MOSFET reliability. Therefore the existing advanced technologies have to be developed to meet desirable performance and reliability requirements