DocumentCode :
2364830
Title :
Hardware implementation of recursive sorting algorithms
Author :
Mihhailov, Dmitri ; Sklyarov, Valery ; Skliarova, Iouliia ; Sudnitson, Alexander
Author_Institution :
Comput. Dept., TUT, Tallinn, Estonia
fYear :
2011
fDate :
25-27 April 2011
Firstpage :
33
Lastpage :
38
Abstract :
The paper describes methods of data sorting in hardware using parallel recursive algorithms over a binary tree. The implementation is based on communicating hierarchical finite state machines interacting with dedicated memories. Distinctive features of the proposed methods are balancing the tree to increase the performance of hardware implementation and the use of sorting networks combined with operations over the tree. Parallel processing is achieved through constructing and traversing different branches of the tree at the same time. The results of prototyping in FPGA and experiments demonstrate applicability and effectiveness of the proposed technique.
Keywords :
field programmable gate arrays; finite state machines; parallel algorithms; sorting; trees (mathematics); FPGA; binary tree branch; data sorting network; hardware implementation; hierarchical finite state machine communication; parallel processing; parallel recursive algorithm; recursive sorting algorithm; tree balancing; Binary trees; Clocks; Field programmable gate arrays; Hardware; Parallel algorithms; Software; Sorting;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Devices, Systems and Applications (ICEDSA), 2011 International Conference on
Conference_Location :
Kuala Lumpur
ISSN :
2159-2047
Print_ISBN :
978-1-61284-388-9
Type :
conf
DOI :
10.1109/ICEDSA.2011.5959040
Filename :
5959040
Link To Document :
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