Title :
Efficient Techniques for Directed Test Generation Using Incremental Satisfiability
Author :
Mishra, Prabhat ; Chen, Mingsong
Author_Institution :
Dept. of Comput. & Inf. Sci. & Eng., Univ. of Florida, Gainesville, FL
Abstract :
Functional validation is a major bottleneck in the current SOC design methodology. While specification-based validation techniques have proposed several promising ideas, the time and resources required for directed test generation can be prohibitively large. This paper presents an efficient test generation methodology using incremental satisfiability. The existing researches have used incremental SAT to improve counterexample (test) generation involving only one property with different bounds. This paper is the first attempt to utilize incremental satisfiability in directed test generation involving multiple properties. The contribution of this paper is a novel methodology to share learning across multiple properties by developing efficient techniques for property clustering, name substitution, and selective forwarding of conflict clauses. Our experimental results using both software and hardware benchmarks demonstrate that our approach can drastically (on average four times) reduce the overall test generation time.
Keywords :
benchmark testing; computability; formal specification; formal verification; integrated circuit design; integrated circuit testing; system-on-chip; directed test generation; functional validation; hardware benchmarks; incremental satisfiability; name substitution; property clustering; selective forwarding; software benchmarks; specification-based validation techniques; system-on-chip design methodology; Automatic testing; Benchmark testing; DC generators; Design engineering; Design methodology; Hardware; Information science; Performance evaluation; Software testing; Very large scale integration;
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-3506-7
DOI :
10.1109/VLSI.Design.2009.72