DocumentCode
2364967
Title
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
Author
Viswanath, Vinod ; Vasudevan, Shobha ; Abraham, Jacob A.
Author_Institution
Comput. Eng. Res. Center, Univ. of Texas at Austin, Austin, TX
fYear
2009
fDate
5-9 Jan. 2009
Firstpage
77
Lastpage
82
Abstract
We present dedicated rewriting, a novel technique to automatically prove the correctness of low power transformations in hardware systems described at the Register Transfer Level (RTL). We guarantee the correctness of any low power transformation by providing a functional equivalence proof of the hardware design before and after the transformation. We characterize low power transformations as rules, within our system. Dedicated rewriting is a highly automated deductive verification technique specially honed for proving correctness of low power transformations. We provide a notion of equivalence and establish the equivalence proof within our dedicated rewriting system. We demonstrate our technique on a non-trivial case study. We show equivalence of a Verilog RTL implementation of a Viterbi decoder, a component of the DRM SoC, before and after the application of multiple low power transformations.
Keywords
formal verification; hardware description languages; rewriting systems; Verilog RTL implementation; Viterbi decoder; automated deductive verification; automatic verification; correctness proving; dedicated rewriting; functional equivalence proof; hardware design; hardware systems; low power transformations; register transfer level; Costs; Databases; Decoding; Design engineering; Hardware design languages; Personal digital assistants; Power engineering and energy; Power engineering computing; Timing; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Design, 2009 22nd International Conference on
Conference_Location
New Delhi
ISSN
1063-9667
Print_ISBN
978-0-7695-3506-7
Type
conf
DOI
10.1109/VLSI.Design.2009.85
Filename
4749656
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