A 20MS/s 5.6 mW 6b Asynchronous ADC in 0.6µm CMOS

The design of an N-comparator based asynchronous successive approximation analog-to-digital converter (SAR ADC) is described (with N = 6) working at 20 MS/sand consuming only 5.6 mW for low power high speed applications like communication systems. Resetting the comparators in each conversion cycle is avoided (reducing power consumption compared to [Chen and Brodersen, 2006]) and only N latches are used overall (incl. comparator latches) for the output code. Further using only N comparators instead of 2^N - 1 as in [der Plas and Verbruggen, 2008], leads to huge savings in terms of area at comparable power consumption. For example, a saving of ~90% comparator area is achieved for the 6 bit ADC design when compared to the design in [der Plas and Verbruggen, 2008].