CMOS based decision directed costas carrier recovery loop (DDC-CRL) for a DSSS communication system

For the discussed DSSS (direct sequence spread spectrum) communication system to be successful, accurate carrier recovery and phase estimation are required in the receiver. This paper presents an analogue DDC-CRL which performs both of these functions as well as the despreading, demodulation and bit detection operations performed by an ideal DSSS receiver. The DDC-CRL presented in this paper operates at bit rates up to 1.53 Mbps and accommodates arbitrary sequence length. The loop operates anywhere over a 20 MHz bandwidth within the 2.4 GHz to 2.4835 GHz ISM (industrial, scientific and medical) band. The DDC-CRL is designed for the 0.35 mum CMOS process from Austria Microsystems (AMS).