DocumentCode
2365139
Title
Two dimensional analytical subthreshold current model of a generic double gate MOSFET with gate underlap
Author
Vaddi, Ramesh ; Dasgupta, S. ; Agarwal, R.P.
Author_Institution
ECE Dept., Indian Inst. of Technol. Roorkee, Roorkee, India
fYear
2011
fDate
25-27 April 2011
Firstpage
246
Lastpage
249
Abstract
A novel analytical model for subthreshold current of a generic double-gate MOSFET (DGMOSFET) with gate-to-source/drain underlaps is proposed. The accuracy of the new model is verified based on comparisons with previously published models and numerical simulation results. With the proposed current model, effectiveness of back gate biasing, back gate asymmetry, gate work function engineering, and gate underlap engineering techniques are evaluated for suppressing the subthreshold leakage currents. Independent gate bias with gate underlap engineering significantly reduces subthreshold leakage currents as compared to standard tied- gate DGMOSFETs.
Keywords
MOSFET; leakage currents; back gate asymmetry; back gate biasing; gate underlap engineering; gate work function engineering; gate-to-source/drain underlaps; generic double gate MOSFET; independent gate bias; subthreshold leakage currents; two dimensional analytical subthreshold current model; Analytical models; Electron devices; Logic gates; MOSFET circuits; Mathematical model; Numerical models; Subthreshold current; Asymmetric double gate MOSFET; Independent gate (4T) DGMOSFET; Tied gate (3T) DGMOSFET; back gate effects; gate underlap engineering; subthreshold current model;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Devices, Systems and Applications (ICEDSA), 2011 International Conference on
Conference_Location
Kuala Lumpur
ISSN
2159-2047
Print_ISBN
978-1-61284-388-9
Type
conf
DOI
10.1109/ICEDSA.2011.5959058
Filename
5959058
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