Title :
Switched-Capacitor Based Buck Converter Design Using Current Limiter for Better Efficiency and Output Ripple
Author :
Das, Tamal ; Mandal, Pradip
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol.-Kharagpur, Kharagpur
Abstract :
In this paper we are addressing power efficiency and output ripple of an embedded switched-capacitor based DC/DC Buck Converters. Here we propose to use current pump based switched-capacitor circuit in buck converter. The current pump circuit limits transition current of the switched-capacitors and hence, improves power efficiency and reduces output ripple. We have also proposed an equivalent macro model of this type of current pump based switched-capacitor converter which would help to get a better essence of the closed loop stability of the system and would reveal clearly trade-offs among load current, flying capacitance and clock frequency. A transistor level implementation of the proposed buck converter in 0.18mu technology is provided. For a load current of 8 mA (maximum)the achieved power efficiency is 72.7% and the output ripple is 27 mV. The flying capacitors in the converter are 2 x 108 pF and the load capacitor is 125 pF.
Keywords :
DC-DC power convertors; charge pump circuits; closed loop systems; current limiters; switched capacitor networks; switching convertors; DC-DC buck converters; clock frequency; closed loop stability; current 8 mA; current limiter; current pump-based switched-capacitor circuit; flying capacitance; load current; output ripple; power efficiency; size 0.8 mum; switched-capacitor based buck converter design; Buck converters; Capacitance; Circuit stability; Clocks; Current limiters; Frequency conversion; Power system modeling; Switched capacitor circuits; Switching circuits; Switching converters; Current Pumping; Hard Switching; Load Regulation; Macro Model; Switched-Capacitor Buck Converter;
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-3506-7
DOI :
10.1109/VLSI.Design.2009.43