• DocumentCode
    2365341
  • Title

    The modern DSP implementation of α-β flight track filter algorithm

  • Author

    Chuan Sheng ; Chaofeng Mi

  • Author_Institution
    Radar Eng. Dept, Air Force Eng. Univ., Xi´an, China
  • fYear
    2010
  • fDate
    26-29 Sept. 2010
  • Firstpage
    274
  • Lastpage
    276
  • Abstract
    This paper is using the basic theory of IIR digital filter and FPGA as hardware implementation to design α-β flight track filter algorithm to implement and realize a modern DSP model. And provide respectful data analysis and simulation results. The advantage of this model is simple and straight forward, pipeline to control easy, computation effective high, fast speed and realtime. This model can be used widely in high data rate radar´s real-time flight track filter application.
  • Keywords
    IIR filters; data analysis; field programmable gate arrays; signal processing; DSP implementation; FPGA; IIR digital filter; data analysis; flight track filter algorithm; hardware implementation; high data rate radar; real-time flight track filter application; α-β flight track filter; FPGA; IIR; modern DSP; pipeline tree;
  • fLanguage
    English
  • Publisher
    iet
  • Conference_Titel
    Wireless, Mobile and Multimedia Networks (ICWMNN 2010), IET 3rd International Conference on
  • Conference_Location
    Beijing
  • Type

    conf

  • DOI
    10.1049/cp.2010.0669
  • Filename
    5703007