DocumentCode :
2365364
Title :
An innovative invert charge recovery logic structure
Author :
Wang, Nan ; Zhang, Yimeng ; Yoshihara, Tsutomu
Author_Institution :
Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan
fYear :
2011
fDate :
25-27 April 2011
Firstpage :
25
Lastpage :
28
Abstract :
In this paper, we propose a new energy saving boost logic structure named Invert Boost Logic(IBL). This design belongs to the Boost Logic family and inherits the same two-phase structure. Transistor numbers, layout area and power consumption reduce significantly by virtue of this novel design. Driven by two opposite phased power clocks, it can maximize its gate drivability by increasing the logic power supply voltage thanks to the recycling ability of the AC energy sources as well as two latches. Energy cut could be as high as 60% at GHz-Class frequencies.
Keywords :
clocks; flip-flops; logic circuits; power aware computing; AC energy source; boost logic family; energy saving boost logic structure; gate drivability; invert boost logic; invert charge recovery logic structure; latch; logic power supply voltage; phased power clock; Clocks; Generators; Logic gates; Power demand; Radiation detectors; Transistors; AC power supply; Boost logic; Charge recovery; Counter;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Devices, Systems and Applications (ICEDSA), 2011 International Conference on
Conference_Location :
Kuala Lumpur
ISSN :
2159-2047
Print_ISBN :
978-1-61284-388-9
Type :
conf
DOI :
10.1109/ICEDSA.2011.5959068
Filename :
5959068
Link To Document :
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