DocumentCode :
2365378
Title :
Exploiting Hybrid Analysis in Solving Electrical Networks
Author :
Sankar, V. Siva ; Narayanan, H. ; Patkar, Sachin B.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Mumbai
fYear :
2009
fDate :
5-9 Jan. 2009
Firstpage :
206
Lastpage :
211
Abstract :
In this paper we use topological hybrid analysis (mixture of nodal analysis and loop analysis) to solve circuits with resistors, voltage sources, current sources and diodes with exponential characteristics. In topological hybrid analysis, from the given network two smaller circuits are derived and solved simultaneously satisfying certain boundary conditions and this results in a solution of the original network. Our main emphasis is on non planar circuits with a large conductance range. The reason for this is that for nonplanar circuits preconditioned Conjugate Gradient method seems to perform very well but its convergence will be adversely affected once the ratio of maximum to minimum conductance becomes as high as 10 raised to 8. To overcome this problem we use Hybrid analysis and a variation of Conjugate Gradient method. Using this method we analyzed circuits containing resistors with large range of values, voltage sources and current sources and having size up to 1 million nodes and 3 million edges on 3 GHZ pentium IV processor with 2 GB RAM in less than 4 minutes. Also, we report the simulation timings for circuits containing diodes.
Keywords :
conjugate gradient methods; diodes; hybrid simulation; resistors; timing circuits; conjugate gradient method; current sources; diodes; electrical networks; loop analysis; nodal analysis; nonplanar circuits; resistors; simulation timings; topological hybrid analysis; voltage sources; Character generation; Circuit analysis; Circuit simulation; Diodes; Equations; Gradient methods; Resistors; Symmetric matrices; Transmission line matrix methods; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
ISSN :
1063-9667
Print_ISBN :
978-0-7695-3506-7
Type :
conf
DOI :
10.1109/VLSI.Design.2009.27
Filename :
4749676
Link To Document :
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