Title :
Low on-resistance LDMOSFETs with DSS (a drain window surrounded by source windows) pattern layout
Author :
Hoshi, Masakatsu ; Shimoida, Yoshio ; Hayami, Yasuaki ; Mihara, Teruyoshi
Author_Institution :
Electron. & Inf. Syst. Res. Lab., Nissan Motor Co. Ltd., Yokosuka, Japan
Abstract :
This paper describes new low on-resistance lateral DMOSFETs having a DSS (a Drain window Surrounded by Source windows) pattern layout. The new DSS pattern layout increases the source cell density to as high as 4 million cells/inch2 thus minimizing the channel-resistance of the devices. A specific on-resistance of 0.65 mΩ·cm2 with a blocking voltage of 36 V is obtained. The DSS LDMOSFETs are suitable for intelligent power devices (IPDs) that provide multiple outputs
Keywords :
electric breakdown; electric resistance; power MOSFET; 36 V; DSS pattern layout; channel resistance; drain window surrounded by source windows; lateral DMOSFET; low on-resistance; source cell density; Costs; Decision support systems; Electrodes; Glass; Information systems; Laboratories; MOSFETs; Silicon; Sputter etching; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1995. ISPSD '95., Proceedings of the 7th International Symposium on
Conference_Location :
Yokohama
Print_ISBN :
0-7803-2618-0
DOI :
10.1109/ISPSD.1995.515010
