Parallel logic simulation on a network of workstations using PVM

Parallel processing is recognized as a practical way to achieve high performance in logic simulation. Instead of using high cost parallel computers or special purpose hardware simulation engines, we explore the implementation of parallel logic simulation on an existing network of workstations using Parallel Virtual Machine (PVM). We carry out a novel parallel implementation of an output event-driven logic simulation algorithm such that a global control processor or workstation is not needed to synchronize the advancement of simulation time to the next time step. Further advantages of our new approach include a random partitioning of the circuit on to available workstations and a pipelined execution of the different phases of the simulation algorithm. To achieve a better load balance we employ a semi-optimistic scheme for gate evaluations such that no rollback is required. The performance of our implementation has been evaluated in real time using the ISCAS combinational and sequential benchmark circuits. Speedups obtained improve with the size of the circuit and the activity level in the circuit. Analyses of the communication overhead shows that the techniques developed here will yield even higher gains as newer networking technologies such as fast and switched Ethernet or ATM are employed to connect workstations