Abstract :
Wafer level packaging (WLP) technology stands at the industry structure interface between the wafer foundry and the assembly and packaging houses. At the same time, it must take full advantage of the symbiotic relationship between different layers of the supply chain for the knowledge base of materials, processes, and equipment from both the semiconductor and assembly industries to develop the inventions and innovations necessary to meet the requirements of the end users. WLCSP is the first WLP technology coming to the market place, and is perhaps the first case of the industry working together in collaboration across various layers of the supply chains. The wafer level chip scale package (WLCSP) has evolved out of a hybridization of other, more established and defined packaging technologies. It combines the metallization and passivation technologies of wafer bumping with the solderball placement technologies of BGA packages. And, through its initial development stages, it has likewise borrowed from the material sets that were used by those packages. However, as the WLCSP has gained acceptance, it has become recognized that the manufacturing and final reliability performance requirements of this package are not always adequately met by the historical material sets that have been used by its predecessor package technologies. Unlike lead frame, BGA, and flip chip in package, which all have either a metal or organic substrate as an interposer; WLCSP attaches the die directly to the circuit board, preferably with no post reflow applied underfill. With WLCSP, only the solderball, and often, a thin layer of polymer, separates the silicon die from the final circuit board assembly. This allows the application of stresses to the die and interface system during both thermal conditioning and mechanical shock that often exceed the fracture strength of the various package materials
Keywords :
assembling; chip scale packaging; metallisation; passivation; polymers; reliability; solders; stress analysis; wafer-scale integration; BGA packages; WLCSP; assembly industries; circuit board assembly; flip chip in package; fracture strength; innovations; inventions; mechanical shock; metallization; organic substrate; package materials; passivation technologies; polymer; reliability performance; semiconductor industries; silicon die; solderball placement technologies; supply chains; thermal conditioning; wafer bumping; wafer foundry; wafer level chip scale package; Assembly; Chip scale packaging; Foundries; Industrial relations; Packaging machines; Printed circuits; Semiconductor device packaging; Supply chains; Thermal stresses; Wafer scale integration;
Conference_Titel :
Advanced Packaging Materials: Processes, Properties and Interface, 200611th International Symposium on