Title :
Low-Power Low-Voltage Analog Circuit Design Using Hierarchical Particle Swarm Optimization
Author :
Thakker, R.A. ; Baghini, M. Shojaei ; Patil, M.B.
Author_Institution :
Dept. of Electr. Eng., Indian Inst. of Technol., Bombay
Abstract :
This paper presents application and effectiveness of Hierarchical particle swarm optimization (HPSO) algorithm for automatic sizing of low-power analog circuits. For the purpose of comparison, circuits are also designed using PSO and Genetic Algorithm (GA). CMOS technologies from 0.35 mum down to 0.13 mum are used. PVT (process, voltage, temperature) variations are considered during the design of circuits. We show that HPSO algorithm converges to a better solution, compared to PSO and GA. For CMOS Miller OTA, even performance of the circuit designed by HPSO algorithm is better than the performance of recently reported manually designed circuit. For the first time, design of this OTA, in 0.4 V supply voltage, is also presented. For this new design, HPSO algorithm has taken 23.5 minutes of CPU time on a Sun system with 1.2 GHz processor and 8 GB RAM.
Keywords :
CMOS analogue integrated circuits; MOSFET; VLSI; genetic algorithms; integrated circuit design; low-power electronics; particle swarm optimisation; CMOS technology; MOS transistor circuit design; frequency 1.2 GHz; genetic algorithm; hierarchical particle swarm optimization; low-power analog circuits; low-voltage analog circuit design; size 0.35 mum to 0.13 mum; supply voltage; time 23.5 min; voltage 0.4 V; Algorithm design and analysis; Analog circuits; CMOS technology; Circuit synthesis; Genetic algorithms; Integrated circuit technology; MOSFETs; Optimization methods; Particle swarm optimization; Voltage; Automatic analog circuit design; hierarchical particle swarm optimization; low-voltage low-power circuits;
Conference_Titel :
VLSI Design, 2009 22nd International Conference on
Conference_Location :
New Delhi
Print_ISBN :
978-0-7695-3506-7
DOI :
10.1109/VLSI.Design.2009.14
